Amplifier circuit with input error compensation

ABSTRACT

An analogue amplifier circuit has a gain stage comprising two differential operational amplifers (17, 18) and an error correction stage comprising two differential operational amplifiers (20, 21) each connected with its inputs across the inputs of a respective gain stage amplifier and its output connected to the non-inverting input of the other gain stage amplifier. A balanced output from the outputs of the two gain stage amplifiers (17, 18) may be provided or these two outputs may be fed to a final stage amplifier (22) to provide a single output.

The present invention relates generally to an analogue amplifier circuitsuitable for a wide range of uses.

It is widely known that analogue amplifier circuits using differentialoperational amplifiers have a disadvantage due to the inherent errorvoltage which appears across the inputs of the differential operationalamplifier. As used hereinafter, the term "operational amplifier" will beunderstood to refer to a differential operational amplifier.

Operational amplifiers have an inverting input and a non-invertinginput. The error voltage arises because in practice the amplifier has afinite gain so that a voltage always appears at the inverting input ofthe amplifier with respect to the non-inverting input. This errorvoltage results in distortion, particularly at low frequencies, whichmakes the operational amplifier unsuitable for circumstances where highfidelity in the amplified signal is required. This is unfortunate sinceoperational amplifiers are ideally suited for use with a balanced lineinput and a balanced line input is almost invariably required for highprecision applications such as in medical apparatus and the like.

Various attempts have been made to compensate for the error voltageappearing across the inputs of an operational amplifier, usuallyachieved by the use of a compensating voltage applied to the output ofthe amplifier. The present invention seeks to provide an amplifiercircuit incorporating an error-correction stage which does not involvethe application of a compensating voltage to the output of a gain stageof the amplifier, but rather which acts to apply compensation at theinput stage thereof.

According to the present invention, therefore, there is provided ananalogue amplifier circuit having a gain stage including two operationalamplifiers, in which the input error of at least one of the operationalamplifiers is compensated by an error correction stage comprising atleast one operational amplifier the inputs of which are connected acrossthe inputs of the said one amplifier of the gain stage and the output ofwhich is connected to the input of the other amplifer of the gain stage.

Preferably the inverting input of the operational amplifier of the errorcorrection stage is connected to the non-inverting input of the said oneoperational amplifier of the gain stage.

Such a circuit is particularly suitable for use in a single line inputmode which is effected by earthing one of two lines of a balanced inputapplied across the inputs of the two amplifiers of the gain stage.

Preferably the output of the operational amplifier of the errorcorrection stage is connected to the non-inverting input of the saidother operational amplifier of the gain stage.

For use with a balanced line input a symmetrical configuration ispreferably employed in which the said error correction stage includes asecond operational amplifier the inputs of which are connected acrossthe inputs of the said other operational amplifier of the gain stage andthe output of which is connected to the input of the said one amplifierof the gain stage. Such a symmetrical configuration thus acts to providea compensating input to each input of a gain stage operational amplifierto compensate for its inherent error voltage.

The two outputs of the two operational amplifiers of the gain stage mayprovide a balanced line output, but if a single line output is requireda final output stage may be provided having differential inputsconnected to respective outputs of the said two operational amplifiersof the gain stage.

In preferred embodiments of the invention the output of the secondoperational amplifier of the error correction stage is connected to thenon-inverting input of the said one operational amplifier of the gainstage and the inverting input of the second operational amplifier of theerror correction stage is connected to the non-inverting input of thesaid other amplifier of the gain stage. Likewise it is preferred thatthe output of each operational amplifier of the error correction stageis connected to the inverting input of the other operational amplifierof the error correction stage. This ensures that the desired gain isachieved by equating the loop gain to unity which leaves a compensationrequirement of a forward gain of unity with a feedback gain also ofunity. These conditions are independent of the overall gain of theamplifier circuit, the overall sign of the gain or the mode ofoperation, that is whether it is differential, single line input orbalanced line input.

Three embodiments of the present invention will now be more particularlydescribed, by way of example, with reference to the accompanyingdrawings, in which:

FIG. 1 is a schematic circuit diagram of a balanced line input amplifierformed as a first embodiment of the present invention;

FIG. 1A is a schematic circuit diagram illustrating a detail of FIG. 1;

FIG. 2 is a circuit diagram illustrating a second embodiment of thepresent invention adapted for a single line input and single lineoutput; and

FIG. 3 is a circuit diagram illustrating a third embodiment of theinvention adapted for a balance line input and single line output.

The circuit shown in FIG. 1 has input terminals 10 and output terminals11, supplying a load 12, and is physically and operationally symmetricalabout an axis running horizontally through the circuit. It has a gainstage 13 within the dashed line 14, and an error correction stage 15within dashed line 16. Each stage includes two operational amplifiers17, 18 and 20, 21, respectively. These may be as produced by NationalSemiconductors, ref LM329.

Each amplifier 20, 21 is connected in a standard circuit configuration,illustrated in FIG. 1A at 22, with four resistors R1 to R4. The gain ofsuch a circuit is R1/R3, and in the present instance for amplifiers 20,21 is set to 1, i.e. R1-R3.

The amplifiers 17, 18 are seen to lie in a similar circuitconfiguration, but with a positive gain defined by RX/RY which can bedecided at will. These two amplfiers lie in parallel across the input10, 11 and the common load 12.

The amplifiers 20, 21 are connected in a feedback loop, and theirnon-inverted and inverted inputs are also connected across the invertedand non-inverted terminals, respectively, of the amplifiers 17, 18,respectively, of the gain stage 13.

It is a known feature of operational amplifiers that an error signalappears at the inverting input on application of an input voltage.Normally, this produces distortion of an analogue signal, which wouldmake the amplifier unusable in normal analogue gain circuits, such asaudio or video amplifiers, for which exact reproduction is required.

The circuit described above overcomes this disadvantage to providelinear analogue gain. This can be admirably illustrated by the verystringent test of amplifying a square wave signal. Normally, there isconsiderable overshoot followed by oscillation at the rising and fallingflanks of the amplified signal. Using the present circuit, the amplifiedsignal is a near perfect reproduction of the input, without any suchdistortions The reasons why the circuit achieves this are unclear, sinceanalysis of the operation of the error correcting stage is extremelydifficult.

In a slight modification an R-C circuit may be added in the feedbackline with RY of the amplifiers 17, 18. This is useful for phonocartridge equalisation.

It will be appreciated, for perfect linearity a similar error correctioncircuit would be required for the differential operational amplifiers20, 21 since they, like the gain stage amplifiers 17, 18, also have aninherent error voltage across their inputs. However, since the error inthe output of the amplifiers 20, 21 is only an error in the compensatingvoltage this is a second order effect and can be considered of minorimportance.

Referring now to FIG. 2 an alternative embodiment adapted for a singleline input and a single line output is shown. In this figure elementshaving the same or corresponding function to corresponding elements inthe embodiment of FIG. 1 have been identified with the same referencenumerals. In the circuit of FIG. 2 the input voltage is applied only toterminal 10, and terminal 11 is grounded. This provides effectively asingle line input which allows the omission of the amplifier 21 in theembodiment of FIG. 1 connected across the inputs of amplifier 18 sincethe error across the amplifier 18 can be regarded as negligible with theinverting input earthed via the terminal 11. The outputs from theamplifiers 17, 18 are fed via respective resistors R5, R6 to theinverting and non-inverting inputs of a further operational amplifier22, which has a negative feedback resistor R7 connected between itsoutput at the zero and the inverting input and a grounded resistor R8connected between the non-inverting input and the resistor R6.

In the embodiment of FIG. 3 a balanced line input is amplified andconverted to a single line output, and the individual components areidentified with the same reference numerals as in the embodiments ofFIGS. 1 and 2. In this embodiment two error correction amplifiers areprovided to produce error correction signals supplied, in each case, tothe non-inverting input of the main gain stage amplifier 17, 18 whilstthe outputs of the two error correction amplifiers 18, 20 are eachconnected to the inverting inputs of the other error correctionamplifier and the non-inverting inputs of the gain stage amplifiers. Theamplifiers 18, 20 have unity gain so that there is unity loop gain andunity forward gain in the circuit to which the inputs of the two gainstage amplifiers are connected. The outputs of the two gain stageamplifiers 17, 18 are connected to respective inputs of a final stageamplifier 22 in a configuration similar to that of the embodiment ofFIG. 2, namely with a non-inverting output. The final stage amplifier 22could, of course, be reversed with the non-inverting input beingconnected to the output of amplifier 17 and the inverting inputconnected to the output of amplifier 18. Likewise, in other embodiments,a single line input mode may be achieved by earthing the terminal 11 asin the embodiment of FIG. 2, retaining the error correction amplifier21.

I claim:
 1. An analogue amplifier circuit having a gain stage includingtwo operational amplifiers, each amplifier providing an output which issubstantially a linear function of an input and wherein the input errorof at least one of the operational amplifiers is compensated by an errorcorrection stage for producing at least a first error correcting signal,the error correction stage comprising at least one operational amplifierthe inputs of which are connected across the inputs of the said oneoperational amplifier of the gain stage and the output of which providesthe first error correcting signal, and is connected to the input of theother operational amplifier of the gain stage.
 2. An analogue amplifiercircuit as claimed in claim 1, in which the inverting input of theoperational amplifier of the error correction stage is connected to thenon-inverting input of the said one operational amplifier of the gainstage.
 3. An analogue amplifier circuit as claimed in claim 1, in whichthe output of the operational amplifier of the error correction stage isconnected to the non inverting input of the said other operationalamplifier of the gain stage.
 4. An analogue amplifier as claimed in anyof claims 1 2 or 3, in which the said error correction stage includes asecond operational amplifier the inputs of which are connected acrossthe inputs of the said other operational amplifier of the gain stage andthe output of which is connected to the input of the said one amplifierof the gain stage.
 5. An analogue amplifier as claimed in claim 4, inwhich the output of the second operational amplifier of the errorcorrection stage is connected to the non-inverting input of the said oneoperational amplifier of the gain stage.
 6. An analogue amplifier asclaimed in claim 4, in which the inverting input of the secondoperational amplifier of the error correction stage is connected to thenon-inverting input of the said other amplifier of the gain stage.
 7. Ananalogue amplifier as claimed in claim 4, in which the output of eachoperational amplifier of the error correction stage is connected to theinverting input of the other operational amplifier of the errorcorrection stage.
 8. An analogue amplifier as claimed in claim 4,further including a final output stage having differential inputsconnected to respective outputs of the said two operational amplifiersof the gain stage.
 9. An analogue amplifier as claimed in claim 3, inwhich one of the two input lines of a balanced input is grounded suchthat the other input line acts as a single line input.
 10. An analogueamplifier as claimed in claim 4, in which:the output of the secondoperational amplifier of the error correction stage is connected to thenon-inverting input of the said one operational amplifier of the gainstage; the inverting input of the second operational amplifier of theerror correction stage is connected to the non-inverting input of thesaid other amplifier of the gain stage; the output of each operationalamplifier of the error correction stage is connected to the invertinginput of the other operational amplifier of the error correction stage;and a final output stage is provided having differential inputsconnected to respective outputs of the said two operational amplifiersof the gain stage.